Takeshi Sugawara

Research Interests

• Cryptography
• Embedded Systems Security
• Hardware Security

Education/Employment

• Bachelor of Engineering (Tohoku University), March 2006.
• Master of Information Science (Graduate School of Information Sciences at Tohoku University), March 2008.
• Internship at Cryptography Research Inc., USA, June 2010–September 2010.
• Ph. D. (Graduate School of Information Sciences at Tohoku University) “A Study on Security Evaluation Techniques for Cryptographic Modules against Physical Attacks”, March 2011.
• Researcher, Information Technology R&D Center, Mitsubishi Electric Corporation, Japan, April 2011–February 2017.
• Visiting Researcher, Ritsumeikan University, Japan, May 2013–March 2015.
• Associate Professor, The University of Electro-Communications, Japan, March 2017—-current.
• Visiting Scholar, University of Michigan, USA, April 2019—-current.

Selected Publications

1. Y. Naito and T. Sugawara, “Lightweight Authenticated Encryption Mode of Operation for Tweakable Block Ciphers,” IACR Trans. Cryptographic Hardware and Embedded Systems 2020(1), to appear eprint.
2. T. Sugawara, N. Shoji, K. Sakiyama, K. Matsuda, N. Miura, and M. Nagata, “Side-Channel Leakage from Sensor-Based Countermeasures against Fault Injection Attack,” Microelectronics Journal, Vol. 90, pp. 63-71, 2019, PDF.
3. T. Sugawara, “3-Share Threshold Implementation of AES S-box without Fresh Randomness,” IACR Trans. Cryptographic Hardware and Embedded Systems 2019(1): 123-145 (2019), PDF.
4. Y. Naito, M. Matsui, Y. Sakai, D. Suzuki, K. Sakiyama, T. Sugawara, “SAEAES,” a Round-1 Candidate of the NIST Lightweight Cryptography project, PDF.
5. K. Matsuda, T. Fujii, N. Shoji, T. Sugawara, K. Sakiyama, Y. Hayashi, M. Nagata, and N. Miura, “A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser against Laser Fault Injection Attack on Cryptographic Processor,” IEEE J. Solid-State Circuits 53(11): 3174-3182 (2018), PDF.
6. Y. Naito, M. Matsui, T. Sugawara, and D. Suzuki, “SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation,” IACR Trans. Cryptographic Hardware and Embedded Systems 2018(2): 192-217 (2018), PDF.
7. S. Nashimoto, D. Suzuki, T. Sugawara, and K. Sakiyama, “Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack,” AsiaCCS 2018: 511-524, PDF.
8. Y. Sasaki, Y. Todo, K. Aoki, Y. Naito, T. Sugawara, Y. Murakami, and M. Matsui, “Minalpher v1.1,” submission to the CAESAR competition, 2015, PDF.
9. T. Sugawara, D. Suzuki, R. Fujii, S. Tawa, R. Hori, M. Shiozaki, T. Fujino, “Reversing Stealthy Dopant-Level Circuits,” In Proc. Cryptographic Hardware and Embedded Systems (CHES 2014), LNCS 8731, Springer-Verlag, pp, 112-126, September, 2014, eprint.
10. T. Sugawara, D. Suzuki, M. Saeki, M. Shiozaki, T. Fujino, “On Measurable Side-Channel Leaks Inside ASIC Design Primitives,” In Proc. Cryptographic Hardware and Embedded Systems (CHES 2013), LNCS 8086, Springer-Verlag, pp. 159-178, August 2013, eprint.
11. M. Knezevic, K. Kobayashi, J. Ikegami, S. Matsuo, A. Satoh, U. Kocabas, J. Fan, T. Katashita, T. Sugawara, K. Sakiyama, I. Verbauwhede, K. Ohta, N. Homma, and T. Aoki, “Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates,” IEEE Trans. VLSI Syst., Vol. 20, Issue 5, pp. 827-840, May 2012.
12. A. Satoh, T. Sugawara, and T. Aoki, “High-Performance Hardware Architectures for Galois Counter Mode,” IEEE Trans. Computers, Vol. 58, Issue 7, pp. 917-930, July, 2009.
13. T. Katashita, A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “Development of Side-Channel Attack Standard Evaluation Environment,” In Proc. European Conference on Circuit Theory and Design (ECCTD2009), IEEE, pp. 403-408, August 2009.
14. A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “High-performance Concurrent Error Detection Scheme for AES Hardware,” In Proc. Cryptographic Hardware and Embedded Systems (CHES2008), LNCS5154, Springer-Verlag, pp. 100-112, August 2008.

Awards

1. Young Researcher Award, Information Processing Society of Japan Tohoku Section, May 2006.
2. Young Researcher Award at Multimedia, Distributed, Cooperative, and Mobile Symposium (DICOMO2007), July 2007.
3. Outstanding Presentation Award at Multimedia, Distributed, Cooperative, and Mobile Symposium (DICOMO2008), July 2008.
4. Outstanding Paper Award at Multimedia, Distributed, Cooperative, and Mobile Symposium (DICOMO2009), July 2009.
5. Outstanding Paper Award, the 12th Computer Security Symposium (co-author), October 2009.
6. Dean’s Award for Excellence, Graduate School of Information Sciences, Tohoku University, March 2011.
7. Young Researcher Award, Information Processing Society of Japan Tohoku Section (co-author), May 2011.
8. Executive Officer’s Award for Excellence, Mitsubishi Electric Corporation, June 2013.
9. Outstanding Presentation Award, Mitsubishi Electric Corporation Technical Committee on Information Technology, April 2014.
10. Outstanding Paper Award, the 32nd Symposium on Cryptography and Information Security (SCIS2015), January 2015.
11. Letter of Appreciation for Collaboration and Technical Excellence (contribution to FIPS140-3 and ISO/IEC 17825 drafts), National Institute of Standards and Technology, United States Department of Commerce, February 2015.
12. Outstanding Presentation Award, Mitsubishi Electric Corporation Technical Committee on Information Technology, April 2015.
13. R&D Center President’s Award for Excellence, Mitsubishi Electric Corporation, June 2015.
14. Outstanding Paper Award, IEICE Technical Committee on Information and Communication System Security (ICSS), June 2015.
15. Outstanding Paper Award, the 33rd Symposium on Cryptography and Information Security (SCIS2016) (co-author), January 2016.
16. Best Poster Award, the 12th International Workshop on Security (IWSEC 2017), September 2017.

Patents

1. S. Nashimoto and T. Sugawara, “Signal Processing Device, Signal Processing Method, and Signal Processing Program,” Application WO2018055748A1.
2. T. Sugawara, “Wireless Communication Device, the Logical Value Selecting Method and a Logical Value Selection Program,” Grant JP6109445B1.
3. H. Fukuda, T. Yoneda, N. Kobayashi, D. Suzuki, M. Misawa, K. Shimizu, and T. Sugawara, “Security Equipment, and Security methods,” Grant JP6103169B1.
4. M. Saeki and T. Sugawara, “Attack Detection Device,” Application WO2016185514A1.
5. T. Sugawara, “Random Number Expanding Device, Random Number Expanding Method, and Non-transitory Computer Readable Recording Medium Storing Random Number Expanding Program,” Grant JP6058245B2．
6. T. Sugawara, “Software Updating Device and Software Update Program,“ Grant JP6053950B2.
7. T. Sugawara, “Semiconductor Device,” Grant JP5976220B2.
8. C. Vuillaume, D. Suzuki, T. Sugawara, and T. Endo, “Semiconductor Device,” Application JP2014145958A.
9. A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “Coding or Decoding Circuit Structure with Error Detecting Capability,” Application WO2009142190A1.

Service

• Program committee, International Workshop on Security (IWSEC), 2013 and 2014.
• Program committee, Smart Card Research and Advanced Application Conference (CARDIS), 2015 and 2016.
• Program committee, Fault Diagnosis and Tolerance in Cryptography (FDTC), 2017–2019.
• Program committee, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2017 and 2018.
• Program committee, Cryptographer’s track at RSA Conference 2019 (CT-RSA2019), 2019.

External Websites

• DBLP
• Google Scholar
• UEC