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研究成果

学術論文(査読あり)

  1. T. Sugawara, N. Shoji, K. Sakiyama, K. Matsuda, N. Miura, and M. Nagata, “Side-Channel Leakage from Sensor-Based Countermeasures against Fault Injection Attack,” Microelectronics Journal, Vol. 90, pp. 63-71, 2019, PDF.
  2. T. Sugawara, K. Sakiyama, S. Nashimoto, D. Suzuki, and T. Nagatsuka, “Oscillator without a Combinatorial Loop and its Threat to FPGA in Data Center,” IET Electronics Letters, 2019 PDF.
  3. T. Sugawara, Y. Li, and K. Sakiyama, “Probing Attack of Share-Serial Threshold Implementation of Advanced Encryption Standard,” IET Electronics Letters, 2019 PDF.
  4. T. Sugawara, “3-Share Threshold Implementation of AES S-box without Fresh Randomness,” IACR Trans. Cryptographic Hardware and Embedded Systems 2019(1): 123-145 (2019), PDF.
  5. K. Matsuda, T. Fujii, N. Shoji, T. Sugawara, K. Sakiyama, Y. Hayashi, M. Nagata, and N. Miura, “A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser against Laser Fault Injection Attack on Cryptographic Processor,” IEEE J. Solid-State Circuits 53(11): 3174-3182 (2018), PDF.
  6. Y. Naito, M. Matsui, T. Sugawara, and D. Suzuki, “SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation,” IACR Trans. Cryptographic Hardware and Embedded Systems 2018(2): 192-217 (2018), PDF.
  7. R. Yashiro, T. Sugawara, M. Iwamoto, and K. Sakiyama, “Q-class Authentication System for Double Arbiter PUF,” IEICE Trans. Fundamentals, Vol. E101-A, No. 1, pp. 129-137, January 2018, PDF.
  8. T. Sugawara, D. Suzuki, and M. Saeki, “Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack,” IEICE Trans. Fundamentals, Vol.E99-A, No.7, pp.1323-1333, July 2016, PDF.
  9. T. Sugawara, D. Suzuki, R. Fujii, S. Tawa, R. Hori, M. Shiozaki, and T. Fujino, “Reversing Stealthy Dopant-Level Circuits,” Journal of Cryptographic Engineering, Vol. 5, Issue 2, Springer-Verlag, pp. 85-94, June 2015.
  10. K. Shimizu, D. Suzuki, T. Tsurumaru, T. Sugawara, M. Shiozaki, and T. Fujino, “Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication,” IEICE Trans. Fundamentals, Vol. 97-A, No. 1, pp. 264-274, January 2014.
  11. T. Sugawara, D. Suzuki, M. Saeki, M. Shiozaki, and T. Fujino, “On Measurable Side-Channel Leaks inside ASIC Design Primitives,” Journal of Cryptographic Engineering, Vol. 4, Issue 1, Springer-Verlag, pp. 59-73, April 2014.
  12. Y. Hayashi, N. Homma, T. Mizuki, T. Sugawara, Y. Kayano, T. Aoki, S. Minegishi, A. Satoh, H. Sone, and H. Inoue, “Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current,” IEICE Trans. Electronics, Vol. E95-C, No. 6, pp. 1089-1097, June 2012.
  13. M. Knezevic, K. Kobayashi, J. Ikegami, S. Matsuo, A. Satoh, U. Kocabas, J. Fan, T. Katashita, T. Sugawara, K. Sakiyama, I. Verbauwhede, K. Ohta, N. Homma, and T. Aoki, “Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates,” IEEE Trans. VLSI Syst., Vol. 20, Issue 5, pp. 827-840, May 2012.
  14. S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments,” IEICE Trans, Fundamentals, Vol. 95-A, No. 1, pp. 263-266, January 2012.
  15. 佐藤証,片下敏宏,菅原健,青木孝文, “ハッシュ関数Luffaのハードウェア実装,” 情報処理学会論文誌, Vol. 52, No. 12, pp. 3755-3765, December, 2011, PDF.
  16. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “High-performance Architecture for Concurrent Error Detection for AES Processors,” IEICE Trans. Fundamentals, Vol. E94-A, No. 10, pp. 1971-1980, October 2011.
  17. S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “An On-chip Glitchy-clock Generator for Testing Fault Injection Attacks,” Journal of Cryptographic Engineering, Vol. 1, Issue 4, pp. 265-270, December 2011.
  18. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “Profiling Attack using Multivariate Regression Analysis,” IEICE Electronics Express, Vol. 7, No. 15, pp. 1139-1144, August 2010, PDF.
  19. 菅原健, 本間尚文, 佐藤証,青木孝文,“ハッシュ関数Whirlpoolの高スケーラブル回路アーキテクチャ,”情報処理学会論文誌, Vol. 50, No. 11, pp. 2618-2632, November 2009. 13, PDF.
  20. A. Satoh, T. Sugawara, and T. Aoki, “High-Performance Hardware Architectures for Galois Counter Mode,” IEEE Trans. Computers, Vol. 58, Issue 7, pp. 917-930, July, 2009.
  21. N. Homma, S. Nagashima, T. Sugawara, T. Aoki, and A. Satoh, “A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks,” IEICE Trans. Fundamentals, Vol. E91-A, No. 1, pp. 193-202, January 2008. 1.

解説論文

  1. 鈴木雅貴, 菅原健, 鈴木大輔, “サイドチャネル攻撃に対する安全性評価の研究動向とEMVカード固有の留意点,” 日本銀行金融研究所機関誌「金融研究」, 第34巻第4号, October 2015. 1, PDF.

国際会議プロシーディングス等(査読あり)

  1. N. Shoji, T. Sugawara, M. Iwamoto, and K. Sakiyama, “An Abstraction Model for 1-bit Probing Attack on Block Ciphers,” IEEE 4th International Conference on Computer and Communication Systems (ICCCS 2019), 2019 (to appear).
  2. R. Matsumura, T. Sugawara, and K. Sakiyama, “A Secure LiDAR with AES-Based Side-Channel Fingerprinting,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), 2018.
  3. Z. Yuan, Y.Li, K. Sakiyama, T. Sugawara, and J. Wang, “Recovering Memory Access Sequence with Differential Flush+Reload Attack,” ISPEC 2018: 424-439
  4. S. Nashimoto, D. Suzuki, T. Sugawara, and K. Sakiyama, “Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack,” AsiaCCS 2018: 511-524, PDF.
  5. K. Matsuda, T. Fujii, N. Shoji, T. Sugawara, K. Sakiyama, Y. Hayashi, M. Nagata, and N. Miura, “A 286F^2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack,” 2018 IEEE International Solid-State Circuits Conference (ISSCC), pp. 352–354, January 2018.
  6. T. Sugawara, N. Shoji, K. Sakiyama, K. Matsuda, N. Miura, and M. Nagata, “Exploiting Bitflip Detector for Non-Invasive Probing and its Application to Ineffective Fault Analysis,” In Proc. Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’17), IEEE, pp. 49-56, September 2017.
  7. N. Shoji, R. Matsumura, T. Sugawara, and K. Sakiyama, “An Evaluation of Ineffective Fault Analysis on AES using Single-Bit Bit-Set/Reset Faults,” Poster Session at the 12nd International Workshop on Security (IWSEC2017), Best Poster Awards, September 2017.
  8. E. Miyamoto, T. Sugawara, and K. Sakiyama, “Efficient Software Implementation of Modular Multiplication in Prime Fields on TI’s DSP TMS320C6678,” In Proc. International Workshop on Information Security Applications (WISA’17), LNCS 10763 Springer-Verlag, pp. 261-273, 2018.
  9. S. Hirose, Y. Naito, and T. Sugawara, “Output Masking of Tweakable Even-Mansour can be Eliminated for Message Authentication Code,” In Proc. Selected Areas in Cryptography (SAC 2016), LNCS vol. 10532, pp. 341–359, Springer-Verlag, 2016.
  10. K. Shimizu, T. Sugawara, D. Suzuki, “PUF as a Sensor,” In Proc. 4th Global Conference on Consumer Electronics (GCCE 2015), IEEE, October 2015.
  11. T. Sugawara, D. Suzuki, M. Saeki, “Two Operands of Multipliers in Side-Channel Attack,” In Proc. 6th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2015), LNCS 9064, Springer-Verlag, pp. 64-78, April 2015, eprint.
  12. T. Sugawara, D. Suzuki, R. Fujii, S. Tawa, R. Hori, M. Shiozaki, T. Fujino, “Reversing Stealthy Dopant-Level Circuits,” In Proc. Cryptographic Hardware and Embedded Systems (CHES 2014), LNCS 8731, Springer-Verlag, pp, 112-126, September, 2014, eprint.
  13. T. Sugawara, D. Suzuki, M. Saeki, M. Shiozaki, T. Fujino, “On Measurable Side-Channel Leaks Inside ASIC Design Primitives,” In Proc. Cryptographic Hardware and Embedded Systems (CHES 2013), LNCS 8086, Springer-Verlag, pp. 159-178, August 2013, eprint.
  14. T. Sugawara, D. Suzuki, T. Katashita, “Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI,” In Proc. Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC2012), IEEE, pp. 16-23, September 2012.
  15. Y. Hayashi, N. Homma, T. Sugawara, T. Mizuki, T. Aoki, and H. Sone, “Non-invasive Trigger-free Fault Injection Method Based on Intentional Electromagnetic Interference,” In Proc. The Non-Invasive Attack Testing Workshop (NIAT 2011), National Institute of Standards and Technology, September 2011.
  16. Y. Hayashi, T. Sugawara, N. Homma, T. Mizuki, T. Aoki, and H. Sone, “Non-Invasive EMI-Based Fault Injection Attack against Cryptographic Modules,” In Proc. International Symposium on Electromagnetic Compatibility (EMC2011), IEEE, pp. 763-767, August 2011.
  17. S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “An On-Chip Glitchy-Clock Generator and its Application to Safe-Error Attack,” In Proc. Second International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2011), pp. 175-182, February 2011.
  18. Y. Hayashi, T. Sugawara, Y. Kayano, N. Homma, T. Mizuki, A. Satoh, T. Aoki, S. Minegishi, H. Sone, and H. Inoue, “Information Leakage from Cryptographic Hardware via Common-Mode Current,” In Proc. International Symposium on Electromagnetic Compatibility (EMC2010), IEEE, pp. 109-114, July 2010 (招待講演).
  19. M. Yamaguchi, H. Toriduka, S. Kobayashi, T. Sugawara, N. Homma, A. Satoh, and T. Aoki, “Development of an On-Chip Micro Shielded-Loop Probe to Evaluate Performance of Magnetic Film to Protect a Cryptographic LSI from Electromagnetic Analysis,” In Proc. International Symposium on Electromagnetic Compatibility (EMC2010), IEEE, pp. 103-108, July 2010 (招待講演).
  20. A. Satoh, T. Katashita, T. Sugawara, N. Homma, and T. Aoki, “Hardware Implementations of Hash Function Luffa,” In Proc. International Symposium on Hardware-Oriented Security and Trust (HOST 2010), IEEE, pp. 130-134, June 2010.
  21. Y. Kim, T. Sugawara, N. Homma, T. Aoki and A. Satoh, “Biasing Power Traces to Improve Correlation in Power Analysis Attacks,” In Proc. First International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2010), pp. 77-80, February 2010.
  22. M. Yamaguchi, H. Toriduka, S. Kobayashi, T. Sugawara, N. Homma, A. Satoh, T. Aoki, “Side Channel Attack to Magnetic Near Field of Cryptographic LSI and its Countermeasure by means of Magnetic Thin Film,” In Proc. 9th Soft Magnetic Materials Conference (SMM19), no. A3-11, September 2009.
  23. T. Katashita, A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “Development of Side-Channel Attack Standard Evaluation Environment,” In Proc. European Conference on Circuit Theory and Design (ECCTD2009), IEEE, pp. 403-408, August 2009.
  24. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “Differential Power Analysis of AES ASIC Implementations with Various S-box Circuits,” In Proc. European Conference on Circuit Theory and Design (ECCTD2009), IEEE, pp. 395-398, August 2009.
  25. T. Sugawara, Y. Hayashi, N. Homma, T. Mizuki, T. Aoki, H. Sone, and A. Satoh, “Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules,” In Proc. World Conference on Information Security Applications (WISA2009), LNCS 5932, Springer-Verlag, pp. 66-78, August 2009.
  26. T. Sugawara, Y. Hayashi, N. Homma, T. Mizuki, T. Aoki, H. Sone, and A. Satoh, “Spectrum Analysis on Cryptographic Modules to Counteract Side-Channel Attacks,” In Proc. International Symposium on Electromagnetic Compatibility (EMC’09), IEICE, pp. 21-24, July 2009.
  27. Y. Hayashi, T. Sugawara, Y. Kayano, N. Homma, T. Mizuki, A. Satoh, T. Aoki, S. Minegishi, H. Sone, and H. Inoue, “An Analysis of Information Leakage from a Cryptographic Hardware via Common-Mode Current,” In Proc. International Symposium on Electromagnetic Compatibility (EMC’09), IEICE, pp. 17-20, July 2009.
  28. T. Katashita, A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “Enhanced Correlation Power Analysis using Key Screening Techniques,” In Proc. International Conference on Reconfigurable Computing and FPGAs (ReConFig’08), IEEE, pp. 403-408, December 2008.
  29. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “Compact ASIC Architectures for the 512-bit Hash Function Whirlpool,” In Proc. World Conference on Information Security Applications (WISA2008), LNCS 5379, Springer-Verlag, pp 28-40, September 2008.
  30. A. Satoh, T. Sugawara, N. Homma, and T. Aoki, “High-performance Concurrent Error Detection Scheme for AES Hardware,” In Proc. Cryptographic Hardware and Embedded Systems (CHES2008), LNCS5154, Springer-Verlag, pp. 100-112, August 2008.
  31. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “High-performance ASIC Implementations of the 128-bit Block Cipher CLEFIA,” In Proc. International Symposium on Circuits and Systems (ISCAS2008), IEEE, pp. 2925-2928, May, 2008.
  32. A. Satoh, T. Sugawara, and T. Aoki, “High-Speed Pipelined Hardware Architecture for Galois Counter Mode,” In Proc. 10th Information Security Conference (ISC2007), LNCS 4779, Springer-Verlag, pp 118-129, October 2007.
  33. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “ASIC Performance Comparison for the ISO Standard Block Ciphers,” In Proc. 2nd Joint Workshop on Information Security (JWIS2007), pp. 485-498, August 2007.
  34. T. Sugawara, N. Homma, T. Aoki, and A. Satoh, “A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128,” In Proc. International Symposium on Circuits and Systems (ISCAS2007), IEEE, pp. 1859-1862, May 2007. 1.

学会口頭発表(査読なし,2017年〜)

  1. 廣瀬勝一, 菅原健, 駒野雄一, “サイドチャネル攻撃への耐性を有する認証暗号方式について,” IT・ISEC・WBS合同研究会, 2019 (to appear).
  2. 藤聡子, 李陽, 崎山一男, 菅原健, “分光スペクトルを用いたLEDの個体識別における電流変化の影響,” 2019年暗号と情報セキュリティシンポジウム (SCIS2019), 3D4-2, 6 pages, (Jan., 2019).
  3. 菅原健, “Changing of the Guards の一般化,” 2019年暗号と情報セキュリティシンポジウム (SCIS2019), 3D3-4, (Jan., 2019).
  4. 高木翼, 崎山一男, 菅原健, 梨本翔永, 鈴木大輔, “SDAccel環境を用いたAES暗号CTRモードの高性能実装,” 2019年暗号と情報セキュリティシンポジウム (SCIS2019), 1D1-1, 7 pages, (Jan., 2019).
  5. 鈴木大輔, 梨本翔永, 永塚智之, 高木翼, 李陽, 崎山一男, 菅原健, “FPGA搭載サーバにおける秘匿アクセラレーション,” 2019年暗号と情報セキュリティシンポジウム (SCIS2019), 1D1-2, 8 pages, (Jan., 2019).
  6. 伊藤駿輔, 菅原健, 崎山一男, 李陽, “AESの指定したラウンド間差分の平文探索アルゴリズムの改良,” IEICE2018年ソサイエティ大会, (Sep., 2018).
  7. 羽田野凌太, 庄司奈津, 李陽, 菅原健, 崎山一男, “AES暗号への故障差分攻撃のモデル化と攻撃回数の評価,” IEICE2018年ソサイエティ大会, (Sep., 2018).
  8. 八代理紗, 藤聡子, 菅原健, 崎山一男, “Arbiter PUFへのサイドチャネルモデリング攻撃の実装と応用,” IEICE2018年ソサイエティ大会, (Sep., 2018).
  9. 西山優太, 李陽, 崎山一男, 菅原健, “様々な実験条件におけるジャイロセンサのセンサなりすまし攻撃に関する基礎的検討,” IEICE2018年ソサイエティ大会, (Sep., 2018).
  10. 藤聡子, 李陽, 崎山一男, 菅原健, “分光器を用いたLEDの個体識別に向けた基礎的研究,” IEICE2018年ソサイエティ大会, (Sep., 2018).
  11. Erina Tatsumi, Kazuo Sakiyama, and Takeshi Sugawara, “A Case Study of Row Hammer under Different Refresh Rates” Poster Session, IWSEC2018, (Aug., 2018).
  12. 松田航平, 藤井達哉, 庄司奈津, 菅原健, 崎山一男, 林優一, 永田真, 三浦典之, “レーザー故障注入攻撃対策を備えた暗号ICの設計手法,” 情報処理学会DAシンポジウム2018 (特別セッション), 6pages, (Aug., 2018).
  13. 八代理紗, 菅原健, 崎山一男, “Arbiter PUFに対する攻撃手法に関する一考察,” 情報処理学会DAシンポジウム2018 (特別セッション), 6pages, (Aug., 2018).
  14. 松田航平, 藤井達哉, 庄司奈津, 菅原健, 崎山一男, 林優一, 永田真, 三浦典之, “基板電流センサと電源瞬断回路を利用した小面積レーザーフォールト注入攻撃対策,” ハードウェアセキュリティ研究会 (HWS), (Apr., 2018).
  15. 松原祐衣子, 宮元冬景, 菅原健,崎山一男, “C66x DSPにおけるペアリングの高速実装,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 2D4-4, 5 pages, (Jan., 2018).
  16. 松村竜我, 菅原健, 崎山一男, “光に重畳したサイドチャネル情報に関する基礎的な解析,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D2-3, 6 pages, (Jan., 2018).
  17. 辰巳恵里奈, 菅原健,崎山一男, “デバイスドライバを用いたRow Hammerのテストツール,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D3-2, 5 pages, (Jan., 2018).
  18. 菅原健, 崎山一男, 梨本翔永, 鈴木大輔, 永塚智之, “パブリッククラウド上のFPGAにおける悪性ハードウェア,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D3-4, 8 pages, (Jan., 2018).
  19. 菅原健, 庄司奈津, 崎山一男, 松田航平, 三浦典之, 永田真, “フォルト検出センサを悪用した非侵襲プロービング攻撃,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D3-6, 3 pages, (Jan., 2018).
  20. 庄司奈津, 菅原健, 岩本貢, 崎山一男, “ブロック暗号へのプロービング攻撃における鍵復元効率の正確な評価モデル,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D3-5, 8 pages, (Jan., 2018).
  21. 梨本翔永, 鈴木大輔, 菅原健, 﨑山一男, “センサフュージョンの攻撃耐性に関するセキュリティ評価,” 2018年暗号と情報セキュリティシンポジウム (SCIS2018), 3D4-1, 8 pages, (Jan., 2018).
  22. Natsu Shoji, Ryuga Matsumura, Takeshi Sugawara, and Kazuo Sakiyama, “An Evaluation of Ineffective Fault Analysis on AES using Single-Bit Bit-Set/Reset Faults,” Poster Session, IWSEC2017, (Aug., 2017).
  23. 辰巳恵里奈, 菅原健, 崎山一男, “Raw Hammerの見える化,” コンピュータセキュリティシンポジウム2017(CSS2017)デモンストレーション(ポスター)セッション, (Oct., 2017).
  24. 松村竜我, 庄司奈津, 菅原健, 崎山一男, “光を用いたサイドチャネル認証,” コンピュータセキュリティシンポジウム2017 (CSS2017)デモンストレーション/ポスター セッション, (Oct., 2017).
  25. 庄司奈津, 松村竜我, 菅原 健, 崎山一男, “誤り暗号文を使わないAESへの故障利用攻撃,” ハードウェアセキュリティ研究会 (HWS), (Jun., 2017).
  26. 松村竜我, 庄司奈津, 菅原健, 崎山一男, “ダイオードレーザーを用いた光によるサイドチャネル認証,” ハードウェアセキュリティ研究会 (HWS), (Jun., 2017).
  27. 辰巳恵里奈, 菅原 健, 崎山一男, “Row Hammerに関する基礎実験,” ハードウェアセキュリティ研究会 (HWS), (Jun., 2017).

その他の発表

講演・チュートリアル・パネルディスカッション等

  1. Y. Naito, M. Matsui, Y. Sakai, D. Suzuki, K. Sakiyama, T. Sugawara, “SAEAES,” a Round-1 Candidate of the NIST Lightweight Cryptography project, PDF.
  2. Y. Naito and T. Sugawara, “Lightweight Authenticated Encryption Mode of Operation for Tweakable Block Ciphers,” Cryptology ePrint Archive: Report 2019/339.
  3. 八代理紗, 菅原健, 岩本貢, 崎山一男, “PUFへの機械学習攻撃と耐性強化に向けて,” PUF技術シンポジウム2018, (Mar., 16th, 2018).
  4. 菅原健, “IoT における機器・ハードウェアへの攻撃の脅威,” 情報セキュリティ・セミナー, 日本銀行・金融研究所, 2017(依頼講演).
  5. 菅原健, “サイドチャネル攻撃と対策,” 2017年ソサイエティ大会, AT3-3, 2017(チュートリアル).
  6. T. Sugawara, “Security issues on the boundary of ideal and real worlds,” Dagstuhl seminar 16441: Adaptive Isolation for Security and Predictability, October 2016 (招待講演).
  7. Y. Sasaki, Y. Todo, K. Aoki, Y. Naito, T. Sugawara, Y. Murakami, and M. Matsui, “Minalpher v1.1,” submission to the CAESAR competition, 2015, PDF.
  8. T. Sugawara, “Recent Results of Dopant-Based Circuit Camouflage Technique,” IEEE Asian Solid-State Circuits Conference (A-SSCC2015), November 2015(招待講演).
  9. T. Sugawara, “Internal Collision Attack on RSA under Closed EM Measurement,” SCIS/CSS invited sessions, The 9th International Workshop on Security (IWSEC2014), August 2014 (招待講演).
  10. T. Sugawara, “Hiding and Finding Circuit in Semiconductor Chip,” Netherlands-Japan Collaborative Cyber Security Conference in Tokyo, November 2015 (招待講演).
  11. T. Sugawara, “What we can see in a chip,” NII Shonan Meeting, 2014, September 2014 (招待講演).
  12. 菅原健, “サイドチャネル攻撃と最近の研究動向,” 2013年ソサイエティ大会, BI1-2, 2013(依頼講演).

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